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@ -48,10 +48,41 @@ class Register: |
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class Acumulator(Register): |
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positive_flag = False |
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negative_flag = False |
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zero_flag = False |
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carry = False |
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carry_flag = False |
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parity_flag = False |
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def add(self, register): |
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def set_flags(self): |
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self.negative_flag = False |
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self.zero_flag = False |
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if self.get_signed() < 0: |
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self.negative_flag = True |
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if self.get() == 0: |
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self.zero_flag = True |
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v = self.get() |
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self.parity_flag = True |
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while v > 0: |
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if (v & 1) == 1: |
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self.parity_flag = not self.parity_flag |
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v >>= 1 |
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def add(self, register: Register): |
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self.value += register.value |
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if self.value.bit_length() > self.n_bits: |
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self.carry_flag = True |
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self.trucate() |
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self.set_flags() |
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def sub(self, register: Register): |
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self.negate() |
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self.add(register) |
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self.negate() |
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self.set_flags() |
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def shift_right(self, through_carry=True): |
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pass |
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def shift_left(self, through_carry=True): |
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pass |