Fixed negate

register.py

@@ -27,8 +27,12 @@ class Register:
     def get(self):
         return self.value
 
+    def complement(self):
+        self.value = self.value ^ ((1 << self.n_bits) - 1)
+
     def negate(self):
-        self.value = ~self.value + 1
+        self.complement()
+        self.value += 1
 
 
 class Acumulator(Register):